VHDL Code For JK Flipflop

Program For JK Flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity jkflipflop is

    Port ( jk : in  STD_LOGIC_VECTOR (1 downto 0);

           clk : in  STD_LOGIC;

           q : out  STD_LOGIC;

           qbar : out  STD_LOGIC);

end jkflipflop;

architecture Behavioral of jkflipflop is

                signal state:std_logic;

begin

                process(jk, clk)

               

begin

                if clk'event and clk='1' then

                case jk is

                                when "00"=>state<=state;

                                when "01"=>state<='0';

                                when "10"=>state<='1';

                                when others=>state<=state;

                                end case;

                                q<=state;

                                qbar<=not state;

                end if;

                end process;

end Behavioral;

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