Saturday 11 August 2012

VHDL Code For SR Flipflop


Program For SR Flip-flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;

entity srff_2 is
    Port ( r : in  STD_LOGIC;
           s : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           q : inout  STD_LOGIC;
           qbar : inout  STD_LOGIC);
end srff_2;

architecture srff_2 of srff_2 is

begin
                process(r,s,clk)
begin
                if clk'event and clk='1' then
                                q <= R NOR qbar;
      qbar <= S NOR q;
                end if;
end process;
end srff_2;

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