VHDL Code For OR Gate

Program for OR Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

              

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

                               

entity or_a is

 Port ( a : in  STD_LOGIC;

 b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end  or_a;

               

architecture Dataflow of or_a is

                begin

                c<=a or b;

end Dataflow;