Tuesday, 4 September 2012

VHDL Code For XOR Gate


Program for XOR Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
               
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
                               
entity xor_a is
 Port ( a : in  STD_LOGIC;
 b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end xor_a;
               
architecture Behavioral of xor_a is
                begin
                c<=a xor b;
end Behavioral;

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