VHDL code for Binary to Gray converter

Below is the VHDL code for  4bit binary to gray code converter. It can done here by using dataflow modelling. You can use the modelling to reverse the conversion eg. Gray to Binary conversion.

CODE FOR 4 BIT Binary To Gray Converter

VHDL Code For XOR Gate

Program for XOR Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

               

VHDL Code For OR Gate

Program for OR Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

              

VHDL Code For D Flip-Flop

Source Code for D-Flipflop :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff1 is
    Port ( data_in : in  STD_LOGIC;
           clock : in  STD_LOGIC;

VHDL Code For JK Flipflop

Program For JK Flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

VHDL Code For T Flipflop

Program For T Flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

VHDL Code For SR Flipflop

Program For SR Flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

VHDL Code For Comparator (4 bit)

4-bit comparator

Source Code of 4-bit comparator :-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity comp1 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);

VHDL Code For 1:4 Demux

Program For 1:4 Demux using Behavioral Modelling:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

VHDL Code For 4:1 Mulitplexer

Program For 4:1 Multiplexer using Behaviroal Modelling:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

VHDL Code For 8:1 multiplexer

Multiplexer is simply a data selector.It has multiple inputs and one output.Any one of the input line is transferred to output depending on the control signal.

This type of operation is usually referred as multiplexing .In 8:1 multiplexer ,there are 8 inputs.Any of these inputs are transferring to output ,which depends on the control signal.For 8 inputs we need ,3 bit wide control signal .

Working:If control signal is "000" ,then the first input is transferring to output line.If control signal is "111",then the last input is transferring

VHDL Code For 2:4 Decoder

Source code for Decoder 2:4:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decod1 is
    Port ( I0 : in  STD_LOGIC;
           I1 : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (3 downto 0));

VHDL Code for 3:8 decoder

Source code for 3:8 decoder:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder3x8 is
Port ( i : in  STD_LOGIC_VECTOR (2 downto 0);
y : out  STD_LOGIC_VECTOR (7 downto 0));
end decoder3x8;

architecture Behavioral of decoder3x8 is

begin

VHDL Code For Encoder (4:2)

Source Code of Binary Encoder 4:2:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encod is
Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
b : out  STD_LOGIC_VECTOR (1 downto 0));
end encod;
 

CODE STRUCTURE OF VHDL

 

Every VHDL code contains at least 3 parts. They are

1 )Library Declaration

2)Entity Declaration

3)Architecture body

Let us discuss these parts in brief

1)LIBRARY DECLERATION

Introduction to VHDL

VHDL is the acronym for Very High Speed Integrated Circuit Hardware Description Laguage.It is a Digital Integrated circuit design tool ,which is widely using now.

There are many tools in IC designing that can be used in place of VHDL(Example Verilog).But VHDL is the most poplar HDL among all HDLs now using in industry.Initially VHDL was developed by U.S Department of Defence.

VHDL Code For Full Adder

Program :-

Program  for full adder-:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

VHDL Code For Half Adder

Program For Half Adder Using Behavioral :-

Program  for half addder-:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

VHDL Code For NOR Gate

Program for NOR Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

               

VHDL Code For XNOR Gate

Program for XNOR Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;