Tuesday, 10 January 2012

VHDL Code For Full Adder



Program :-
Program  for full adder-:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;




-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_addera is
    Port ( a : in  STD_LOGIC_VECTOR (2 downto 0);
                          sum : out  STD_LOGIC;
                                         carry : out  STD_LOGIC);
end full_addera;
               
architecture Behavioral of full_addera is

begin
                process (a)
begin
                if a="000" then
                                sum<= '0';
                                carry<='0';
                elsif a="001" then
                                sum<= '1';
                                carry<= '0';
                elsif a="010" then
                                sum<= '1';
                                carry<= '0';
                elsif a="011" then
                                sum<= '0';
                                carry<= '1';
                elsif a="100" then
                                sum<= '1';
                                carry<= '0';
                elsif a="101" then
                                sum<='0';
                                carry<='1';
                elsif a="110" then
                                sum<='0';
                                carry<='1';
                elsif a="111" then
                                sum<= '1';
                                carry<= '1';
                else
                                sum<='0';
                                carry<='1';
                end if;

                end process;
end Behavioral;
 ==========================================================================================
Truth table of full adder :-

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