Monday, 9 January 2012

VHDL Code For Half Adder


Program For Half Adder Using Behavioral :-
Program  for half addder-:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
               
entity half_addera is
                 Port ( a : in  STD_LOGIC_VECTOR(1 downto 0);
                     sum : out  STD_LOGIC;
                   carry : out  STD_LOGIC);
end half_addera;

architecture Behavioral of half_addera is

begin
                process (a)
begin
                if a="00" then
                                sum<= '0';
                                carry<='0';
                elsif a="01" then
                                sum<= '1';
                                carry<= '0';
                elsif a="10" then
                                sum<= '1';
                                carry<= '0';
                else
                                sum<='0';
                                carry<='1';
                end if;
               
                end process;
end Behavioral;

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