Thursday, 5 January 2012

VHDL Code For NOT Gate


Program for NOT Gate:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
               

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
                               
entity not_a is
 Port ( a : in  STD_LOGIC;
 b : out  STD_LOGIC);
end not_a;
               
architecture Dataflow of not_a is
                begin
                b<= not a;
end Dataflow;

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