VHDL Code For 1:4 Demux

Program For 1:4 Demux using Behavioral Modelling:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity demux_14a is

    Port ( y : in  STD_LOGIC;

           s : in  STD_LOGIC_VECTOR (1 downto 0);

           a,b,c,d : out  STD_LOGIC);

end demux_14a;

architecture Behavioral of demux_14a is

begin

process(s,y)

begin

if s="00" then

                a<=y;

elsif s="01" then

                b<=y;

elsif s="10" then

                c<=y;

else

                d<=y;

end if;

end process;

end Behavioral;