VHDL Code For 4:1 Mulitplexer

Program For 4:1 Multiplexer using Behaviroal Modelling:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux_41a is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : in  STD_LOGIC;

           d : in  STD_LOGIC;

           s : in  STD_LOGIC_VECTOR (1 downto 0);

           o : out  STD_LOGIC);

end mux_41a;

architecture Behavioral of mux_41a is

begin

process(s,a,b,c,d)

begin

if s="00" then

                o<=a;

elsif s="01" then

                o<=b;

elsif s="10" then

                o<=c;

else

                o<=d;

end if;

end process;

end Behavioral;