VHDL Code For T Flipflop

Program For T Flip-flop:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity tflipflop_2 is

    Port ( t : in  STD_LOGIC;

           clk : in  STD_LOGIC;

           q : inout  STD_LOGIC;

           qbar : out  STD_LOGIC);

end tflipflop_2;

architecture Behavioral of tflipflop_2 is

begin

            process(clk,t)

            begin

                        if (clk = '1' and clk'event) then

                                case T is

                                                when ‘0’=>state<=’1’;

                                                when  ‘1’=>state<=’0’;

                                end case;

                     end if;

            end process;

end Behavioral;