VHDL Code for 3:8 decoder

Source code for 3:8 decoder:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder3x8 is
Port ( i : in  STD_LOGIC_VECTOR (2 downto 0);
y : out  STD_LOGIC_VECTOR (7 downto 0));
end decoder3x8;

architecture Behavioral of decoder3x8 is

begin

process(i)
begin
case i is
when "111" => y<="00000001";
when "110" => y<="00000010";
when "101" => y<="00000100";
when "100" => y<="00001000";
when "011" => y<="00010000";
when "010" => y<="00100000";
when "001" => y<="01000000";

when "000" => y<="10000000";
when others => null;
end case;
end process;
end Behavioral;
Truth table of 3:8 decoder:-