VHDL Code For AND Gate

Program for AND Gate:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

               

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

                               

entity and_a is

 Port ( a : in  STD_LOGIC;

 b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end and_a;

               

architecture Dataflow of and_a is

                begin

                c<=a and b;

end Dataflow;

Check Syntax:-

 

View of RTL Schematic:-

Test Bench Waveform:-

Feedback Us and like us  on facebook